# #modelsim #waveform #quartus
Вопрос:
Я действительно новичок в Quartus и ModelSim, я могу запускать моделирование функций в modelsim, но это не загрузка окна только для чтения, в котором я могу видеть вывод. Есть ли какое-либо место, где создается файл только для чтения для просмотра вывода? Или в любом случае вытащить его? Вот окно выполнения потока моделирования:
Using: /home/yash/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off intro_to_quartus -c intro_to_quartus --vector_source="/home/yash/intelFPGA_lite/20.1/quartus/intro_to_quartus/xor_sim1.vwf" --testbench_file="/home/yash/intelFPGA_lite/20.1/quartus/intro_to_quartus/simulation/qsim/xor_sim1.vwf.vt"
Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Sun Sep 19 12:45:24 2021Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off intro_to_quartus -c intro_to_quartus --vector_source=/home/yash/intelFPGA_lite/20.1/quartus/intro_to_quartus/xor_sim1.vwf --testbench_file=/home/yash/intelFPGA_lite/20.1/quartus/intro_to_quartus/simulation/qsim/xor_sim1.vwf.vtWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/yash/intelFPGA_lite/20.1/quartus/intro_to_quartus/simulation/qsim/" intro_to_quartus -c intro_to_quartus
Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Sun Sep 19 12:45:26 2021Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=/home/yash/intelFPGA_lite/20.1/quartus/intro_to_quartus/simulation/qsim/ intro_to_quartus -c intro_to_quartusWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file intro_to_quartus.vo in folder "/home/yash/intelFPGA_lite/20.1/quartus/intro_to_quartus/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 712 megabytes Info: Processing ended: Sun Sep 19 12:45:27 2021 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
**** Generating the ModelSim .do script ****
/home/yash/intelFPGA_lite/20.1/quartus/intro_to_quartus/simulation/qsim/intro_to_quartus.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
/home/yash/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do intro_to_quartus.do
Я приношу свои извинения, если мой вопрос или язык выглядят неправильно, я также новичок в этой платформе.