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Я пытаюсь реализовать счетчик MOD-5 в VHDL и попытался выполнить следующие действия:

• Я создал GENERIC счетчик N бит
• Затем я создал экземпляр 3-битного счетчика
• Используя 3-разрядный счетчик в качестве COMPONENT счетчика, я сбрасываю счетчик на 0, когда он достигает 4

Я протестировал его, и он не работает, сигнал счетчика остается неопределенным для всей симуляции. Может ли кто-нибудь решить эту проблему?

 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY counter_n_bit IS
GENERIC(
    N : INTEGER);
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    -- Clear is a synchronous reset
    Clear : IN STD_LOGIC;
    Count : BUFFER UNSIGNED(N - 1 DOWNTO 0)
    );
END counter_n_bit;

ARCHITECTURE behaviour OF counter_n_bit IS

BEGIN

    PROCESS(Clock)
    BEGIN
        -- since this is a synchronous circuit, signal should
        -- only change on clock's edges. I chose rising edges.
        IF Clock'EVENT AND Clock = '1' THEN
            -- if clear is set to 1, no matter the other signals, the counter resets
            -- same if it got to the max integer that can be represented on N bits (2^N - 1)
            IF Clear = '1' OR Count = 2**N - 1 THEN
                Count <= (OTHERS => '0');
            ELSE
            -- if none of this condtions are satisfied we're in the regular case
            -- and I update the Count value incrementing it by one
                IF Enable = '1' THEN
                    Count <= Count   1;
                END IF;
            END IF;
        END IF;
    END PROCESS;

END behaviour;
 

 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY counter_3_bit IS
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    Clear : IN STD_LOGIC;
    Count : OUT UNSIGNED(2 DOWNTO 0)
    );
END counter_3_bit;

ARCHITECTURE behaviour OF counter_3_bit IS

COMPONENT counter_n_bit 
GENERIC(
    N : INTEGER);
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    Clear : IN STD_LOGIC;
    Count : OUT UNSIGNED(N - 1 DOWNTO 0)
    );
END COMPONENT;

BEGIN
    -- instantiation of a 3 bit counter
    counter_3: counter_n_bit GENERIC MAP (N => 3) PORT MAP (Clock => Clock, Enable => Enable, Clear => Clear, Count => Count);

END behaviour;
 

 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY counter_3_bit_5 IS
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    Clear : IN STD_LOGIC;
    Count : BUFFER UNSIGNED(2 DOWNTO 0)
    );
END counter_3_bit_5;

ARCHITECTURE behaviour OF counter_3_bit_5 IS

COMPONENT counter_3_bit 
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    Clear : IN STD_LOGIC;
    Count : OUT UNSIGNED(2 DOWNTO 0)
    );
END COMPONENT;

BEGIN
    -- instantiation of a 3 bit counter
    counter_3: counter_3_bit PORT MAP (Clock => Clock, Enable => Enable, Clear => Clear, Count => Count);
    
    PROCESS (Count)
    
    BEGIN

        IF Count = "100" THEN
            Count <= "000";
        END IF;

    END PROCESS;


END behaviour;
 

 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY tb_counter_3_bit_5 IS
END tb_counter_3_bit_5;

ARCHITECTURE behaviour OF tb_counter_3_bit_5 IS

COMPONENT counter_3_bit_5 
PORT(
    Clock : IN STD_LOGIC;
    Enable : IN STD_LOGIC;
    Clear : IN STD_LOGIC;
    Count : BUFFER UNSIGNED(2 DOWNTO 0)
    );
END COMPONENT;

SIGNAL Clock_tb, Clear_tb, Enable_tb : STD_LOGIC;
SIGNAL Count_tb : UNSIGNED(2 DOWNTO 0);

BEGIN

    Clear_tb <= '1', '0' AFTER 6 ns;
    Enable_tb <= '1';

    clk_process: PROCESS
    BEGIN
        Clock_tb <= '0';
        WAIT FOR 5 ns;
        Clock_tb <= NOT Clock_tb;
        WAIT FOR 5 ns;
    END PROCESS;
    -- instantiation of a 3 bit counter
    dut: counter_3_bit_5 PORT MAP (Clock => Clock_tb, Enable => Enable_tb, Clear => Clear_tb, Count => Count_tb);

END behaviour;